works on this processor. Suppose you executed the code below on a After the execution of the program, the content of memory location 3010 is. (d) What is the sign extend doing during cycles in which its output is not needed? What fraction of all instructions use the sign extender? You'll get a detailed solution from a subject matter expert that helps you learn core concepts. predictor determine which of the two repeating patterns it is *** I hope you like the answer *** Answer: Given: R-type = 24% I-type = 28% LIMA= 25% = 10% CBZ = 11% B = 2% 1 Fraction of Data memory utilized: The instructions . 4 this exercise, we examine in detail how an instruction is [5] c) What fraction of all instructions use the sign extend? systems. Problems in this exercise refer to a clock cycle in which the processor fetches the following, 0000 0000 1100 0110 1011 1010 0010 0011 in 32 bit. (Check your these instructions has a particular type of RAW data dependence. /Filter /FlateDecode of instructions, and assume that it is executed on a five-stage What fraction of all instructions use the sign extend? CLRA.D. What fraction of all instructions use instruction memory? executed in a single-cycle datapath. cost/complexity/performance trade-offs of forwarding in a int compare_and_swap(int *word, int testval, int newval) interrupts in pipelined processors", IEEE Trans. the following two instructions: Instruction 1 Instruction 2 The type of RAW data dependence is identified by the stage that fault. 4 importance of having a good branch predictor depends on Explain the reasoning for any "don't care control signals. 4.13.2 Assume there is no forwarding, indicate hazards. A: The CPU gets to memory as per an unmistakable pecking order. follows: 4.16[5] <4> What is the clock cycle time in a pipelined is the utilization of the data memory? 3- What fraction of all instructions do not Load: 20% 4.9[10] <4> What is the speedup achieved by adding LDUR STURCBZ B 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? not used? How often while the pipeline is full do we have a add x6, x10, x instruction to RISC-V. A: Given the following memory values and a one-address machine with an accumulator,Word 20 contains, A: Given question has asked to identify the units that are utilized by given instructions:- To figure this out, we need to determine the slowest instruction. What fraction of all instructions use data memory? // remaining code is executed? In taht, case, the improvement would be well worth the additional 4.4% additional cost (as, Examine the difficulty of adding a proposed lwi.d rd, rs1, rs2 (Load With Increment) instruction. 4.27[20] <4> For the new hazard detection unit from 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? Register File. 3.3 What fraction of all instructions use the sign extend? Consider the following instruction mix: A: What is the name of the size of a single storage location in the 8086 processor? 4.32[5] <4, 4, 4> How much energy is spent to As a result, the Approximately how many stalls would you expect this structural hazard to generate in a, typical program? Justify your formula. According to diagram 4.19, the sign extension block is not connected to logic. The CPI increases from 1 to 1.4125. return oldval; [5] d) What is the sign extend doing during cycles in which its output is not needed? What is the CPI for each option? stages (including paths to the ID stage for branch resolution). control signal and have the data memory be read in every the ALU unit? detection, insert NOPs to ensure correct execution. (relative to the fastest processor from 4.26) be if we added or x13, x15, x A: Actually, there are 8 addressing modes are used. How many NOPs (as a, percentage of code instructions) can remain in the typical program before that program. $p%TU|[W\JQG)j3uNSc 4.10[5] <4>What is the speedup achieved by adding 3.1 What fraction of all instructions use data memory? instruction memory? pipeline design. m~~ ^8pO}m*cdU/`{q E>sx36*yH9^Q^;x{Fa+` of the register block's write port? Question: 3. branches with the always-taken predictor? In this exercise, to n. (In 4.21.2, x was equal to .4.) The latency is 300+400+350+500+100 = 1650ps. A program residing in the memory unit of a computer consists of a sequence of, A: The components of a computer usually only communicate with the CPU. If not, explain why not. sign extend? Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% (a) What fraction of all instructions use data memory? A. sw will need to wait for add to complete the WB stage. [5] b) What fraction of all instructions use instructions memory? to determine if a particular fault is present. not allowed to pass through the ALU above must now have a data path to write data 2. Data memory is used in SW and LW as we are writings and reading to memory. (d) What is the sign extend doing during cycles in which its output is not needed? beqz x11, LABEL ld x11, 0(x12) or x15, x16, x17: IF. Problems in this exercise refer to pipelined /ColorSpace /DeviceRGB You can assume that the other components of the jalENT 4.3 Consider the following instruction mix: . (Use the instruction mix from Exercise 4.) or x15, x16, x17: IF ID. Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% (a) What fraction of all instructions use data memory? percentage of code instructions) must a program have before What would the final values of register x15 be? (See Exercise 4.) Write about: /Group 2 0 R What is the sign extend doing during cycles in which its output not needed? Register setup is the amount of time a, registers data input must be stable before the rising edge of the clock. The code above uses the following registers: Assume the two-issue, statically scheduled processor for this exercise has the (Begin with, The importance of having a good branch predictor depends on how often conditional branches, are executed. (b) What fraction of all instructions use instruction memory? The value of $6 will be ready at time interval 4 as well. Can you design a LEGV8 assembly code: free instruction memory and data memory to let you make code that will produce a near-optimal speedup. This is often called a stuck-at-0 4.5[10] <4> For each mux, show the values of its inputs WAI., A: ALU stands for Arithmetic and Logical which acts as brain of a computer and it is called so because, A: Introduction: 5 0 obj << 3- What fraction of all instructions do not use 4.1[5] <4>What are the values of control signals generated performance of the pipeline? By how much? ALU, but will reduce the number of instructions by 5% andi. spent stalling due to mispredicted branches. sd x13, 0(x15) (b) What fraction of all instructions use instruction memory? 4.21[10] <4> Repeat 4.21; however, this time let x represent pipelined processor. The memory location; and Data memory. with a k stage pipeline? 4.7.3 What is the clock cycle time if we must support ADD, BEQ, LW, and SW instructions? (i., how long must the clock period be to ensure that this Your answer will be with respect to x. 4.11[5] <4> Which new data paths (if any) do we need The Gumnut can also address I/O devices using up to 256 input ports and 256 output ports. 4.11[5] <4> Which existing functional blocks (if any) 4.33[10] <4, 4> If we know that the processor has a ), What is the primary factor that influences whether a program will run faster or slower on, Do you consider the original CPU (as shown in Figure 4.21) a better overall design; or do. 4.7[5] <4> What is the latency of an R-type instruction 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? What fraction of all instructions use instruction memory? be a structural hazard every time a program needs to fetch an } Conditional branch: 25% Highlight the path through which this value is You'll get a detailed solution from a subject matter expert that helps you learn core concepts. silicon) and manufacturing errors can result in defective Can you use a single test for both stuck-at-0 and FLOATING POINT: IR+RR+FPU+WR : 700, 10%5. oLAPTc in which its output is not needed? Fetch c. Suppose that (after optimization) a typical n- instruction program requires an. thus it doesn't matter what is the value of "memtoreg",since it will not be. Write) = 1010 ps. In old CPU each instruction needs, 5 clocks for its, Average CPI = 0.52*4 + 0.25*5 + 0.11*4 + 0.12*3, Average CPI = 2.08 + 1.25 + 0.44 + 0.36 = 4.13, Consider the addition of a multiplier to the CPU shown in Figure 4.21. next A: Answer: Option B: No, since we are using RISC processor, only LOAD and STORE instructions can access, A: Answer :- Compare&Swap: x]s8+t 3AGovv7f&^`$l18~HlfM H:znAWoDTcF@719UH)GK):m\eeT ',rU6&|%FQ(:N`\Ve^aiiFC* You can use. if (oldval == testval) 4.27[5] <4> If there is no forwarding or hazard exception handling mechanism. instruction during the same cycle in which another instruction accesses data. 4 exercise explores how exception handling affects branch predictor accuracy, this will determine how much time is Nguyen Quoc Trung. In order to execute a machine instruction the, A: STR is used to store something from the register to memory.For Example:STR r2,[r1] -The instruction, A: Given that: of operations in this compute. useful work. oldval = *word; class of cross-talk faults is when a signal is connected to a Given the cost/performance ratios you just calculated, describe a situation where it, makes sense to add more registers and describe a situation where it doesnt make, It does not make sense from a mathematical point of view to add more registers because, the new CPU costs more per unit of performance. 6600 , Glenview, IL: Scott, Foresman. 4.11[5] <4> Which new functional blocks (if any) do we 20 b. Repeat Exercise 4. 4.25[10] <4> Show a pipeline execution diagram for the A very common defect is for one wire to affect the 4.5[10] <4> What are the values of all inputs for the Consider the following instruction mix 1. a) What fraction of all instructions use data memory? We have to decide if it is better to forward only from the b. Instruction: and rd, rs1, rs Select an answerA) 0.6.sB) 6msC)6usD) 60us, In the Compare&Swap instruction, why must the instruction execute atomically? program runs slower on the pipeline with forwarding? CliffsNotes study guides are written by real teachers and From the above set we can see it is a s-type instruction, ALU control takes ALUop and Instructions [30,14-12], What is the new PC address after this instruction is executed? 4 given the instruction mix below? following RISC-V assembly code: Indicate hazards and add nop instructions to eleminate them. An incorrectly predicted branch will cause three, instructions to be flushed: the instructions currently in the IF, ID, and EX stages. 4.6[10] <4> List the values of the signals generated by the 4.5[10] <4> What are the input values for the ALU and BranchAdd produces output that is not used for this and AND instruction, ONLY is useful. Comparing both: (cost & performance) so cost is defined depend on total parts with, = (1000+10+10+200+10+100+300+30+200+600+30)/1430, = (1000 =800+10+2000+100+30+10+10+500+30) / 1430, Difference of cost(/unit) = (without multiplier - with multiplier), Ratio of performance= Cost of improvement / cost of without improvement, When processor designers consider a possible improvement to the processor datapath, the. control unit for addi. Experts are tested by Chegg as specialists in their subject area. Suppose that you are debating whether to buy or lease a new Chevy Spark, which is worth $13,000. first five cycles during the execution of this code. BEQ, A: Maximum performance of pipeline configuration: [5] 2. 4.4 What fraction of instructions use the Address . See Section 4.7 and Figure 4.51 for, x15 = 54 (The code will run correctly because the result of the first instruction is written, back to the register file at the beginning of the 5, reads the updated value of x11 during the second half of this cycle. However, the mux will ignore the input because the control is signaling the ALU to use the Register's read data 2 instead. MOV AX, BX Similarly, ALU and LW instructions use the register block's write port. This is often called a stuck-at-0 fault. Processor(1) zh - Please give as much additional information as possible. Student needs to show steps of the solution. MemToReg wire is stuck at 0? thus it will not matter where the data is taken from since that data is not. Hint: this input lets your the program longer and store additional data. 3.4 What is the sign extend doing during cycles in which. 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? ld x29, 8(x16) First week only $4.99! z}] = l:SO'YcxwO~2O8 S5>LG'7?wiy30? This communication is carried, A: Algorithm to add two16 bit Number 3. 4.33[10] <4, 4> Repeat Exercise 4.33 for a stuck-at- BRANCH: IR+RR+ALU : 270, 20%1 cycle is 780ps = .780 nanoseconds for this machine, on the assumption thatall instructions take 1 cycle (assume all memory access is in cache). processor is designed. 4.21[10] <4> Can a program with only .075*n NOPs 100 ps to the latency of the full-forwarding EX stage. 4 exercise is intended to help you understand the If 25% of. require modification? Use of solution provided by us for unfair practice like cheating will result in action from our end which may include 4.13.3 Assume there is full forwarding. Repeat 4.21.2; however, this time let x represent the number of NOP instructions relative. version of the pipeline from Section 4 that does not handle data. Justify your formula. Which new data paths (if any) do we need for this instruction? A. Pipelined processor clock cycle is the longest stage (500ps), whereas non-pipelined is the sum of all stages (1650ps). instructions trigger? In this case, there will add x13, x11, x14: IF ID EX. given. 4.1[5] <4>Which resources (blocks) perform a useful 4.3 Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 4.3.1 [5] <4.4>What fraction of all instructions use data memory? ld x11, 0(x12): IF ID EX ME WB print_al_proc, A: EXPLANATION: (a) What additional logic blocks, if any, are needed to add I-type instructions to the single-cycle processor shown in Figure 1? The following operations (instruction) function with signed numbers except one. possibly run faster on the pipeline with forwarding? thus "memtoreg" is don't care in case of "sd" also. in the pipeline when the first instruction causes the first code above will stall. TOP: slli x5, x12, 3 The Control Data there are no data hazards, and that no delay slots are used. Can a program with only .075*n NOPs possibly run faster on the pipeline with, At minimum, how many NOPs (as a percentage of code instructions) must a program. by the control in Figure 4 for this instruction? 400 (I-Mem) + 30 (Mux) + 200 (Reg. stream A: answer for a: School of Advance Business & Commerce, Lahore, What are the values of control signals generated by the control in Figure 4.10 for this. This is a data hazard (MEM/WB.RegisterRd), 1 2 3 4 5 6 7 (Time Interval). This addition will add 300, ps to the latency of the ALU, but will reduce the number of instructions by 5% (because there. In this exercise, we examine in detail how an instruction is executed in a single-cycle datapath. 4.7.4 In what fraction of all cycles is the data memory used? instruction in terms of energy consumption? 2- What fraction of all instructions use 2 Problems in this exercise Every instruction must be fetched from instruction memory before it can be executed. What is the minimum clock period for this CPU? 4 this exercise we compare the performance of 1-issue and Problems in this exercise assume that the logic blocks used to implement a processors, (Register read is the time needed after the rising clock edge for the new register value to, appear on the output. /SMask 12 0 R (Check your you consider the new CPU a better overall design? Interpretation: Reg[Rd] = Reg[Rn] AND Reg[Rm]. instructions are loads, what is the effect of this change on always register a logical 0. Since these can both be forwarded to the sw EX stage at time interval 5, no stalling (or nops) are needed. OR AL, [BX+1] predicted instructions have the same chance of being replaced. 25% Start your trial now! 4.7.6 If we can improve the latency of one of the given datapath components by 10%, which component should it be? 4.7[5] <4> What is the latency of beq? Consider the following instruction mix: 4.3.1 [5] <4.4>What fraction of all instructions use data memory? EX ME WB, 4 the following loop. For each of these exceptions, specify the Opcode is 00000001. In general, is it possible to reduce the number of stalls/NOPs resulting from this, Must this structural hazard be handled in hardware? Load instructions are used to move data in memory or memory address to registers (before operation). datapaths from Figure 4. Show the pipeline { Decode of bits. How might familism impact service delivery for a client seeking mental health treatment? Assume that correctly and incorrectly. If we know that 80%, of all executed branch instructions are easy-to-predict loop-back branches that are, always predicted correctly, what is the accuracy of the 2-bit predictor on the remaining. What is this circuit doing in cycles in which its input is not needed? 4.26[5] <4> What would be the additional speedup A: Which of the following is a main memory? ME WB Smith, J. E. and A. R. Plezkun [1988].